High-voltage semiconductor devices may generally have a vertical structure since they require a high voltage compared with complementary metal oxide semiconductor (CMOS) devices. For example, in fabricating a CMOS, voltage of about 1.5V may be used. On the other hand, in fabricating high-voltage devices, voltage of 10 to 100V, preferably, 30V may be used. For the purpose of forming a vertical structure, after a deep trench structure is formed, doped polysilicon may then be deposited to form a vertical gate electrode. For such a vertical structure of a high-voltage device, a source region and an upper boundary surface on and/or over which polysilicon is deposited may exist on the same plane. When the device operates after an electrode is formed in the source region, it may be necessary to prevent current conduction of the source region and the polysilicon upper boundary surface.
As illustrated in example FIG. 1A, a process of fabricating a semiconductor high-voltage device may include forming a thermal oxide film as hard mask 102 on and/or over the entire surface of a silicon substrate such as semiconductor substrate 100.
As illustrated in example FIG. 1B, a photolithography process may then be performed on hard mask 102, thus forming photoresist patterns 104 defining a gate electrode region.
As illustrated in example FIGS. 1C and 1D, hard mask 102 may then be patterned by performing a dry etch process employing photoresist patterns 104 to from hard mask patterns 102′. The underlying semiconductor substrate 100 may then be patterned, thus forming deep trenches A. In example FIGS. 1C and 1D, reference numerals 100′ and 102′ denote the semiconductor substrate and the hard mask, respectively, after the patterning process.
As illustrated in example FIG. 1E, gate oxide film 104 may then be formed with respect to substrate 100′ and hard mask 102′ on which the patterning process has been performed. Polysilicon layer 106 may then be deposited on and/or over the entire surface, thereby gap-filling trenches A having gate oxide film 104 formed therein.
As illustrated in example FIG. 1F, a portion of polysilicon layer 106 may then be removed by performing an etchback process on polysilicon layer 106. At this time, a portion of hard mask 102′ may also be removed. In example FIG. 1F, reference numerals 102″ and 106′ denote the hard mask and the polysilicon, respectively, after the etchback process.
As illustrated in example FIG. 1Q all the remaining hard mask 102″ and a portion of polysilicon layer 106′ after the etchback process may then be removed by performing an etching process. In example FIG. 1G reference numeral 106″ denotes polysilicon after the dry etch process. In removing hard mask 102″ using the dry etch process, a portion of gate oxide film 104 within trenches A may also be removed. As illustrated from reference numeral L of example FIG. 1G, a portion of gate oxide film 104 can be etched, and thus, lost. This is because both hard mask 102″ and gate oxide film 104 have the same oxide film structure.
As described above, phenomena such as the leakage current can occur due to etching of the gate oxide film for isolating source/drain regions and a polysilicon region. Accordingly, device characteristics are degraded, which may result in a problem that a current path changes after subsequent source/drain region is formed.